Ethernet IP & Verification for AI-Scale Networking
AI clusters are Ethernet's most demanding customer—pushing the industry toward higher per-lane rates, tighter FEC trade-offs, and UEC-aligned transport.
Ethernet architecture, layer by layer.
MAC – framing, addressing, flow control
PCS – 64b/66b encoding, scrambling, lane distribution
FEC – Reed-Solomon, mandatory at PAM4, latency/reliability trade-off
Auto-negotiation & link training – startup handshake, bring-up failures
PMA/PMD & SerDes – multi-lane physical, 112G/224G PAM4
Packet logic
↓
[ MAC ]
framing · addressing · flow control
↓
[ PCS ]
64b/66b encode · scramble · distribute across N logical lanes
↓
[ FEC (RS) ]
correction blocks · latency/reliability trade-off
↓
[ PMA / SerDes ]
N physical lanes · 112G/224G PAM4
↓
channel (copper / optics)
alignment markers · lane deskew
112G-class / 224G-class PAM4
Where SNOVA contributes.
Ethernet IP development – MAC, PCS, FEC, AN/LT, PHY interfaces
Design & integration – subsystem architecture to tape-out
Verification – UVM environments, coverage, debug, sign-off
NIC & switch verification – endpoint and fabric devices
Interoperability – multi-vendor, multi-speed, multi-media
UEC alignment – backward/forward compatibility and signaling
Our verification journey.
1.
Specification
2.
Architecture
3.
RTL
4.
Simulation
5.
Coverage
6.
Compliance
7.
FPGA
8.
Interoperability
9.
Sign-off
spec deltas & test-plan extraction
lane maps, FEC modes
design/integration
coverage-driven UVM benches
functional + assertion closure
spec compliance campaigns
at-speed prototypes vs. real partners
AN/LT against third-party gear
evidence package
Why this matters for AI clusters.
AI workloads demand synchronized, low-latency all-to-all collectives at scale. Ethernet evolution increases bandwidth per port and lanes—while tightening the margin for signal integrity, FEC latency, and tail-latency sensitivity.
| 100G-era | 400G-era | 800G-era | 1.6T-era | |
|---|---|---|---|---|
| Lane rate class | 25G NRZ | 50G PAM4 | 100G-class PAM4 | 200G-class PAM4 |
| Lanes per port | more lanes and/or faster lanes → | |||
| PCS | encoding + alignment complexity grows with lane count and rate → | |||
| FEC | optional | RS-FEC standard | mandatory | tighter latency / coding-gain trade-offs |
Auto-negotiation & link training in the field.
Link initialization
↓
Capability exchange
ability pages: rates, FEC modes
↓
Priority resolution
speed/FEC selection
↓
Link training
per-lane TX tuning
↓
Link-up
Debug path
☑ check advertised abilities
☑ FEC mismatch
☑ lane polarity/swap
☑ training timeout
Field failures cluster at startup — before the link ever comes up.
| Challenge | Why it's hard | How it's retired |
|---|---|---|
| PAM4 signaling | Tight eye margins, ISI, crosstalk at 100G/200G lane rates | Channel-aware modeling, equalization, TX/RX tuning, margining |
| FEC latency | RS-FEC adds latency and interacts with queueing & cut-through | FEC partitioning, early-decode, latency budgeting, workload validation |
| Lane alignment | Alignment markers and deskew across many lanes | Robust marker detect, elastic buffers, lane fault tolerance |
| Deskew | Skew variation with PVT, temperature, and media | Adaptive deskew, elastic buffers, stress across corners |
| Auto-negotiation | Capability mismatches, mode fallbacks, timer issues | AN matrix validation, fallback paths, timer/timeout verification |
| Link training | Training convergence, polarity/swap, coefficient stability | Per-lane tuning verification, restart logic, negative testing |
| Interoperability | Multi-vendor behavior differences and spec gray areas | Broad partner testing, AN/LT matrices, spec-driven closure |
| Error injection | Hard to hit rare corner cases in silicon | Error/CRC/FEC injection, scoreboard & recovery validation |
The Road to 1.6T Ethernet: PCS, FEC, and What Changes at 224G SerDes
A deep dive into 224G-class PAM4, PCS evolution, and FEC trade-offs on the path to 1.6T.
PCIe Generation-over-Generation Verification
Lessons from AN/LT bring-up and interoperability that carry over to Ethernet.
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Let's discuss your Ethernet MAC, PCS, FEC IP and verification needs.
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