UALink Design & Verification
An open standard for the fabric inside the pod.
AI models are trained across pods of accelerators that must behave like one machine. UALink is the open-standard answer for the scale-up fabric inside the pod—delivering the memory-semantic communication these applications require.
POD
Accelerator
Accelerator
Accelerator
Scale-up switch
Accelerator
Accelerator
Accelerator
NIC
NIC
Host CPU
Ethernet / UEC (scale-out) →
Cluster
network
network
UALink
memory-semantic
read/write
between accelerators
memory-semantic
read/write
between accelerators
←───→
Every hop counts —
sub-μs
sub-μs
←───→
Microsecond-class,
packet semantics
packet semantics
One diagram, two domains: UALink inside the pod, Ethernet/UEC beyond it.
The problem UALink addresses.
Scale-up ≠ scale-out
Memory-semantic operations at far lower latency. Ethernet was not designed for this domain.
Ecosystem openness
An open standard lets vendors mix silicon the way PCIe and Ethernet did.
Architecture headroom
Pod sizes, topology, switch radix, and implementation decisions interact with the fabric spec.
| Characteristic | UALink | Ethernet UEC |
|---|---|---|
| Domain | Scale-up | Scale-out |
| Connectivity | Accelerator-to-accelerator | Node / rack / cluster |
| Communication model | Memory-semantic (load/store) | Network / transport (packets) |
| Typical distance | Intra-pod (short) | Inter-node (longer) |
| Primary challenge | Low latency, high bandwidth | Scale, traffic, reliability |
InfiniBand
Widely deployed scale-out fabric for HPC and AI clusters.
PCIe
Ubiquitous host–device interface inside the node.
UCIe
Chiplet and die-to-die interconnect for adjacent silicon.
A system architecture question is rarely “which one?” — it is “which one, where?”
Where SNOVA contributes.
Scale-up architecture engineering
Endpoint integration, topology selection, and implementation choices that fit workload and silicon constraints.
Design
RTL design and integration for UALink protocol logic with clean interfaces and reuse in mind.
Verification
Protocol-level environments, compliance test planning, and coverage that targets real failure modes.
Adjacent-stack fluency
Ethernet/UEC and UCIe context so UALink verification is never an isolated activity.
UALink lifecycle.
1.
Specification
review
review
2.
Fabric
architecture
architecture
3.
RTL
design
design
4.
Verification
environment
environment
5.
Compliance
test plan
test plan
6.
System
integration
integration
7.
Bring-up &
interop
interop
UALink expertise is scarce; the specification is young and the engineers who understand both the spec and silicon-level implementation realities are few.
Related reading
ARTICLE
Scale-Up vs Scale-Out: How UALink and Ethernet Divide the AI Fabric
A practical look at when to use UALink, when to use Ethernet/UEC, and how they complement each other.
Read article →