Three layers.
Three different problems.
One engineering discipline.
Modern AI infrastructure moves data across three connectivity domains — each with its own distance, devices, protocol needs, and verification challenges. SNOVA brings end-to-end expertise from protocol to silicon so your programs ship.
host I/O · attaches accelerators, NICs, storage to the CPU
complex
SCALE-OUT
Ethernet / UEC
east-west AI traffic across thousands of nodes
switch ASICs, NICs
switch ASICs, NICs
SNOVA: IP · design · verification
SCALE-UP
UALink
memory-semantic, intra-pod
accelerator I/O + switch silicon
accelerator I/O + switch silicon
SNOVA: IP · design · verification
DIE-TO-DIE
UCIe / custom LLD
millimetres of reach, extreme bandwidth density
PHYs, adapters, chiplet SoCs
PHYs, adapters, chiplet SoCs
SNOVA: IP · design · verification
Compute: RISC-V • Edge AI
metres–kilometres
centimetres–metres
millimetres
Treating these layers as interchangeable is how programs slip.
Scale-out —
Ethernet / UEC
Cluster-wide networking for thousands of nodes carrying bandwidth-hungry AI traffic. Built on switch ASICs and NICs. SNOVA’s role: MAC, PCS, FEC, AN design and verification.
Scale-up —
UALink
Accelerator-to-accelerator connectivity within a pod. Memory-semantic, low latency, high bandwidth. SNOVA’s role: design and verification of UALink IP and systems.
Die-to-die —
UCIe / custom LLD
Chiplet interconnect inside the package. Millimetre-scale reach, extreme bandwidth density. SNOVA’s role: UCIe PHY and compliance, adapter and interop solutions.
Host I/O —
PCIe
The host interface that attaches devices and subsystems to the CPU complex. SNOVA’s role: PCIe IP verification across generations.
Ethernet / UEC
Cluster-wide AI networking at rising per-lane rates
UALink
Memory-semantic accelerator fabric within a pod
UCIe & Chiplets
Die-to-die interconnect and chiplet interop
PCIe Verification
Protocol depth and gen-over-gen compliance
RISC-V
Application-specific processing and SoC integration
Edge AI
Real ML workloads on constrained local hardware
Protocol-to-Silicon Hierarchy
licensable implementation of any of these
1
Protocol / Standard
packet formats, state machines, timing
↓
2
Controller
digital logic implementing upper layers
↓
3
PCS
encoding, lane alignment, FEC
↓
4
PHY (SerDes)
physical-layer bits on the wire
↓
5
IP
licensable, integrable implementation
↓
6
Silicon
chip integrating IP + compute + memory + I/O
↓
7
Verification
proves implementation matches protocol
What the terms mean
1
Protocol / Standard: The specification that defines behavior and timing.
2
Controller: Implements the protocol logic and manages data flow.
3
PCS: Prepares data for transmission with encoding and error control.
4
PHY (SerDes): Converts bits to signals and transmits over the medium.
5
IP: Reusable block or core that can be integrated into designs.
6
Silicon: The final chip where IP, compute, and I/O come together.
7
Verification: Ensures the silicon behaves exactly as the protocol requires.
| Attribute | Ethernet / UEC | UALink | UCIe | PCIe | RISC-V | Edge AI |
|---|---|---|---|---|---|---|
| Domain | Scale-out | Scale-up | Die-to-die | Host I/O | Compute | Compute |
| Distance | Metres–kilometres | Centimetres–metres | Millimetres | Centimetres | On-chip | On-device |
| Primary purpose | Cluster networking | Accelerator connectivity | Chiplet interconnect | Host connectivity | General purpose compute | Local inference |
| Typical devices | Switches, NICs | Switches, accelerators | Chiplets, adapters | Root complex, devices | CPUs, SoCs | MCUs, NPUs |
| Protocol character | Packet-based | Memory-semantic | Transaction-based | Packet + transaction | ISA / instruction set | Workload-specific |
| Key engineering challenge | Scale & per-lane rate | Low latency & bandwidth | Density & compliance | Compatibility & compliance | Performance & extensibility | Power & efficiency |
| SNOVA capability | MAC, PCS, FEC, AN | IP design & verification | PHY, adapters, interop | PCIe IP verification | RISC-V enablement | Edge AI optimization |
Ethernet, UALink, UCIe, and PCIe are not interchangeable.
They solve different problems at different distances with different semantics.
They solve different problems at different distances with different semantics.
Have a program in one of these layers?
Let's talk through your architecture and verification needs.