PCIe Verification Services
The interface every AI system still depends on.
PCIe is the most ubiquitous high-speed interface in modern silicon. Each generation doubles bandwidth while making verification harder — tighter timing, deeper protocol state, FLIT modes, PAM4 signaling.
PCIe verification is rarely the glamorous part. It is very often the schedule-critical part.
1
Transaction Layer
TLP formation/parsing · ordering rules · flow-control credits · completions/timeouts
↓
2
Data Link Layer
sequence numbers · ACK/NAK · replay buffer · DLLPs
⚠ framing & retry semantics change in FLIT mode
↓
3
Logical PHY
LTSSM states · ordered sets · link training & equalization · lane/rate negotiation · scrambling/encoding
↓
4
Physical Interface
electrical/SerDes boundary
⚠ SI/analog domain — outside functional-verification scope, inside interop scope
verification
covers
covers
Each layer has its own state space; the bugs live at the seams — and in the power states.
WHAT PCIe VERIFICATION INVOLVES
Protocol verification across the layer stack
Transaction, data link, logical PHY.
Verification IP (VIP) deployment
Testbenches around commercial or in-house VIP; knowing where defaults hide gaps.
Compliance-oriented testing
Spec-aligned test plans and checklists.
Functional coverage
Protocol state space coverage models, closure tied to sign-off.
Error and stress scenarios
Injected link errors, replay storms, malformed TLPs, surprise link-down, power races.
Interoperability
Behavior against real link partners and switches.
METHODOLOGY FLOW
1.
Specification
2.
Test Plan
3.
Testbench
4.
VIP
5.
Stimulus
6.
Assertions
7.
Coverage
8.
Error Injection
9.
Compliance
10.
Interoperability
11.
Sign-off
spec-delta capture
feature/negative matrix
env architecture
configure + know its gaps
constrained-random + directed
protocol invariants
functional coverage
fault campaigns
checklist alignment
real link partners
evidence package
Coverage tells you when you're done; error injection tells you whether you'd survive being wrong.
GENERATIONAL EXPERTISE
PCIe verification expertise is generation-specific: what constitutes a credible test plan changes with each spec revision.
Our engineers have lived through multiple generations — we know where risk moves, what new features change, and how to focus verification where it matters most.
SIGN-OFF CHECKLIST (WHAT GOOD LOOKS LIKE)
| 1 | Protocol functionality | All mandatory and optional features verified to spec. |
| 2 | Ordering | Completion and non-completion ordering rules. |
| 3 | Flow control | Credits, updates, and consumption across paths. |
| 4 | Credits | Advertised credits, return path, corner conditions. |
| 5 | ACK/NAK | Correct acknowledgments and NAK error handling. |
| 6 | Replay | Replay buffer behavior and recovery correctness. |
| 7 | Error handling | Malformed TLPs, poison, ECRC, and timeouts. |
| 8 | Link training | LTSSM, lane training, equalization, rate negotiation. |
| 9 | Power management | ASPM states, L0s/L1/L1.2, L0p (Gen6). |
| 10 | Surprise link-down | Recovery from unexpected link loss. |
| 11 | Coverage | Adequate coverage closure on all critical models. |
| 12 | Compliance | Spec-aligned test plan execution and checklist closure. |
| 13 | Interoperability | Interop with real partners and switches. |
The Gen6-specific version — FLIT mode, FEC-with-retry, L0p — is in the article.
RISK MATRIX (WHAT CAN GO WRONG)
| Risk | Example failure | Detection method | Sign-off evidence |
|---|---|---|---|
| Protocol-state escape | Unexpected state transition or illegal TLP sequence | Assertions, state coverage, directed negative tests | State coverage closure, assertion zero failures |
| Credit accounting bug | Credits leak or underflow under stress | Random stress, scoreboarding, credit monitors | No credit mismatches in long runs |
| Replay/FEC interaction | Replay storm or FEC + retry corner breaks link | Fault injection, replay stress, mode-switch tests | Successful recovery across scenarios |
| Power-state race | Link fails to exit low-power state cleanly | Power state randomization, exit timing tests | Reliable entry/exit across all states |
| Interop divergence | Works with one partner, fails with another | Multi-partner interop matrix | Pass across approved partner matrix |
WHERE PCIe SITS
CPUs expose it to the platform.
GPUs and accelerators attach through it.
NICs, DPUs, and storage depend on it.