1
Transaction Layer
TLP ordering · flow control · credits · 14-bit tags (scaled for BDP)
2
Data Link Layer — FLIT mode
fixed 256-byte flits · flit-granularity seq/ack/replay · DLLPs in flits
NEW: FLIT mode replaces variable framing
Gen6 NEW FEATURE: FLIT mode
3
Logical PHY
LTSSM · equalization at 64 GT/s · precoding · L0p width scaling
NEW: L0p power state — live width change
Gen6 NEW FEATURE: L0p power state
4
Physical Interface
PAM4 64 GT/s · lightweight FEC + strong CRC + replay
NEW: PAM4 + FEC/CRC — errors are routine
Gen6 NEW FEATURE: PAM4 + FEC/CRC
Executive Summary
PCIe 6.0 doubles to 64 GT/s with PAM4, lightweight FEC+CRC+replay, mandatory FLIT mode, and L0p. A Gen5 testbench is not a Gen6 testbench with a faster clock. This is the sign-off checklist.
What actually changed, and why verification cares
PAM4 + FEC + CRC + replay (errors as mainline path)
PAM4 increases raw bandwidth, but also bit error rate. Gen6 mandates lightweight FEC ahead of a strong CRC, with replay for misses. Error handling is no longer an exception — it's the normal path.
FLIT mode (256-byte fixed flits, no 128b/130b framing)
Variable-size TLP/DLLP traffic is packetized into 256-byte FLITs. CRC and FEC operate at flit granularity: Sequence/ACK/Replay are carried in FLITs. No more 128b/130b framing or variable packet boundaries.
L0p (live width scaling without link-down)
The link can change width on-the-fly under load (entry/exit L0p). Training, lane margining, and flow control must survive width changes without dropping the link.
FLIT mode vs. pre-Gen6 framing
Pre-Gen6 (variable framing era)
TLP —
TLP — idle —
DLLP —
TLP
Variable-size packets (TLP/DLLP) with 128b/130b tokens and electrical idle gaps
Gen6 (FLIT mode)
FLIT 256B
CRC
FEC
FLIT 256B
CRC
FEC
FLIT 256B
...
Continuous train of 256B FLITs with CRC and FEC — no electrical idle gaps
The rest inherits: Equalization, precoding, flow control, deeper tags, and backward compatibility still matter — and now operate in a FLIT world.
PCIe Gen6 Sign-off Checklist
1 Logical PHY / Link Training
LTSSM full-state & arc coverage at 64 GT/s
Equalization phases, bypass paths, timeout arcs
Rate changes across all supported speeds
Recovery under training failures; degraded-width
Lane margining hooks functional
2 FLIT / Data Link (Gen6 new)
Flit packing/unpacking: TLP straddle, NOP flits, malformed detection
Seq/ack/replay at flit granularity; replay storms
FEC/CRC/replay interplay: correction, CRC-catch, retry under load
DLLP-equivalents in flit form: FC updates, PM messages
3 Transaction Layer
Ordering matrix under stress across FLIT boundaries
Credit accounting: init, updates, starvation, rollover; 14-bit tags
Malformed/poisoned TLP handling; AER logging
4 Power Management (L0p)
L0p: entry/exit under load, width-change corners, retry/FC interaction
Legacy L-state races retained from prior gens
5 System / Integration
Surprise link-down: containment, status, software recovery
Interop against real partners/switches; compliance alignment
Error-Injection Matrix (make errors routine)
| Injection | Expected machinery | Pass evidence |
|---|---|---|
| Single-symbol errors (within FEC capability) | FEC corrects → CRC passes → no replay | Counters show FEC corrections; no replay spikes |
| Burst errors exceeding FEC capability | CRC detects → replay requested → recovery | CRC-catch logged; replay succeeds; data intact |
| Replay-buffer pressure / storm | Throttling, flow control, fairness preserved | No deadlock; forward progress under load |
| Error during L0p width change | Width change completes; no FLIT/ACK loss | Width-change events pass; no link-down |
| Training-phase fault injection | Recovery to L0; proper fallbacks | LTSSM returns to L0; errors contained |
| Flit grammar corruption | Malformed flit detected; recovery path | AER logged; no data corruption to host |
Coverage and Evidence: What sign-off should demand
- Feature-to-coverage map: LTSSM, FLIT grammar, FEC/CRC/replay, L0p.
- Flit-granularity assertions: seq/ack/replay correctness, ordering, credit compliance.
- Closure reports + waiver log: justified, reviewed, and risk-ranked.
- Error-campaign results: matrix above with KPIs and trends.
- Interop plan & results: real partners, switches, and compliance tools.
☆
If the evidence can't show the FEC-miss path and an L0p width change under load, it isn't a Gen6 sign-off.
“” SNOVA Perspective
Gen transitions shift where the pain lives. In Gen6, the pain moved into error handling and live-width state. Teams that win invest early in FLIT-aware scoreboards, FEC/replay error campaigns, and L0p stress — then automate it. That's how we help customers retire verification debt and ship on time.
Conclusion
Gen6 is not a faster Gen5. PAM4 makes errors routine; FEC+CRC+replay makes handling them mainline; FLIT changes grammar; L0p adds live-width state. Verify like that, and your sign-off will hold in the real world.
Facing a Gen6 sign-off?
Talk with our engineers about verification plans and testbench readiness.
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