| 100G-era | 400G-era | 800G-era | 1.6T-era | |
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25G NRZ | 50G PAM4 | 100G-class PAM4 | 200G-class PAM4 / 224G SerDes |
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optional | RS-FEC standard | mandatory | tighter latency / coding-gain trade-offs |
1.6T Ethernet is not “800G but bigger.” The defining change is 200 Gb/s-per-lane signaling (224G-class SerDes) under IEEE P802.3dj — rippling through lane count, FEC architecture, PCS structure, and verification.
The problem: the lane is the product
Port rate = lanes × lane rate. Doubling lane rate (100G → 200G) shrinks PAM4 SNR margin, turning errors into a managed flow. The system solution is a new balance across FEC strength, latency, and verification.
Architecture: what each sublayer does
- MAC: frames, flow control, and timing closure at the system boundary.
- PCS: 256b/257b transcode, alignment markers, lane distribution, deskew.
- FEC: RS(544,514) with interleaving spreads bursts; segmented/concatenated modes trade latency vs. coding gain.
- PMA/SerDes: 224G-class PAM4 lanes with DSP-heavy equalization and precoding block bursts before FEC.
• lane distribution
• deskew
| Aspect | 100G-class-lane era (400G/800G) | 200G-class-lane era (800G/1.6T) |
|---|---|---|
| Per-lane signaling | 25G/50G/100G (NRZ/PAM4) | 200G-class PAM4 (224G SerDes) |
| Lanes for flagship port | 8 (400G), 8 (800G) | 8 (800G), 8 (1.6T) |
| Channel margin | More comfortable | Tighter; more sensitive to loss, ISI, crosstalk |
| FEC posture | RS(544,514), moderate interleaving | RS(544,514), deeper interleaving; segmented/concatenated options |
| Error statistics | Lower burst length and density | Longer/denser bursts expected |
| PCS | 64b/66b → 256b/257b, simpler alignment | Heavier alignment, more deskew stress |
| Verification center of gravity | Golden path, random errors | Burst modeling, loss/deskew, corner-heavy |
Practical implications
At SNOVA, we build Ethernet MAC/PCS/FEC IP and verification environments that scale with lane rate. Our focus on standards, auto-negotiation robustness, and coverage-driven verification helps teams ship 224G SerDes-based designs with confidence and predictable schedules.
Conclusion
1.6T Ethernet is defined by 200G per lane. That single change reshapes channel margin, FEC strategy, PCS complexity, and verification. Design for it end-to-end, verify it early, and your path to 1.6T will be boring — in the best way.
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1. Enumerate shipped configurations: rates × lane maps × FEC modes — kill combinatorial explosion by contract
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2. Model bursty error statistics in stimulus; verify FEC correction, exhaustion, and marker-loss recovery
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3. Close functional coverage on PCS state machines: alignment lock/loss/relock, deskew limits, BIP/AM handling
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4. Treat SerDes digital interface as formal contract: widths, valid/ready semantics, status, reset ordering
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5. Stage interoperability: VIP → FPGA vs. real partners → silicon plugfest, with AN/LT in every stage