check advertised abilities • FEC mismatch • lane polarity/swap • training timeout • restart AN
The mechanism in one page
- Clause 73 AN: ability pages and priority resolution decide what both sides can do — not what you hoped they'd do.
- Clause 72/136 link training: per-lane transmit tap adjustment and eye measurement over multiple iterations.
- PCS lock: alignment markers, deskew, and FEC synchronization complete the handshake.
Three phases. Three ways to fail.
The failure classes we keep meeting
- 1 FEC resolution surprises
- 2 Forced-mode asymmetry
- 3 Polarity/lane-map surprises
- 4 Training timeouts on marginal channels
- 5 Breakout/media configuration mismatch
- 6 Module management state machines
- 7 Version-skew interpretation gaps
Quick takeaways
The seven failure classes, in practice
| Failure class | Typical symptom | First check |
|---|---|---|
| 1 FEC resolution surprises | Negotiated FEC weaker than expected (e.g., none) | Compare resolved vs. configured FEC both sides |
| 2 Forced-mode asymmetry | Link only comes up when both sides forced | AN enable/disable and ability parity |
| 3 Polarity/lane-map surprises | High errors or no lock on some lanes | Lane polarity, lane swap, lane maps |
| 4 Training timeouts on marginal channels | Training fails after N attempts | Per-lane SNR/eye, Tx tap range, EQ settings |
| 5 Breakout/media configuration mismatch | No link or unstable across breakouts | Port mode, breakout config, device role |
| 6 Module management state machines | Delays or flaps during AN/LT | Module state, firmware, low-power modes |
| 7 Version-skew interpretation gaps | Works with one partner, not another | Firmware/doc versions, errata, capabilities |
Debug method: converge, don't thrash
Record both sides: AN on/off, abilities, FEC, lane maps, breakout, module firmware. Half of "AN bugs" die here.
Dump AN status/resolved registers both sides. Confirm agreement before touching training.
Force rate/FEC both sides → Isolate AN vs Training vs PCS → Reintroduce AN last
Training status, polarity, error counters lane-by-lane; map failures to routing.
One capture of AN pages/training frames settles interpretation arguments.
A fix against one partner is a hypothesis. Matrix across partners, media, configurations.
Design and verification implications
- Bring-up pain is a pre-silicon decision.
- Build per-lane observability (status, counters, tap, EQ).
- Cover AN/LT state machines and timeouts in verification.
- Prototype on FPGA against real partners early.
- Write the runbook during verification, not at bring-up.
The SNOVA perspective
AN/LT is the seam where SNOVA works: MAC/PCS/FEC logic meeting real partners in the field. We invest in:
- Complete state-machine coverage and negative testing
- Partner-asymmetry models and interop matrices
- FPGA platforms to reproduce issues before silicon
Better coverage. Fewer surprises. Faster time-to-link.
Conclusion
AN doesn't break because the mechanism is bad; it breaks because it's the meeting point of every configuration decision two vendors made independently.